1 ps8590c 09/22/04 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2972 description the pi6c2972 are 3.3v compatible, pll based clock driver devices targeted for high-performance cisc or risc processor based sys- tems. with output frequencies of up to 125 mhz and skews of 550ps the pi6c2972 are ideally suited for most synchronous systems. the devices offer twelve low skew outputs plus a feedback and sync output for added flexibility and ease of system implementation. the pi6c2972 features an extensive level of frequency programma- bility between the 12 outputs as well as the input vs output relationships. using the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock edge prior to the coincident edges of the qa and qc outputs. the sync output will indicate when the coincident rising edges of the above relationships will occur. the power?on reset ensures proper programming if the frequency select pins are set at power up. if the fselfb2 pin is held high, it may be necessary to apply a reset after power?up to ensure synchroni- zation between the qfb output and the other outputs. the internal power?on reset is designed to provide this function, but with power?up conditions being dependent, it is difficult to guarantee. all other conditions of the fsel pins will automatically synchronize during pll lock acquisition. the pi6c2972 offers a very flexible output enable/disable scheme. note that all of the control inputs on the pi6c2972 have internal pull? up resistors. the pi6c2972 is fully 3.3v compatible and requires no external loop filter components. all inputs accept lvcmos/lvttl compatible levels while the outputs provide lvcmos levels with the capability to drive 50-ohm transmission lines. for series terminated lines each pi6c2972 output can drive two 50-ohm lines in parallel thus effec- tively doubling the fanout of the device. features ? fully integrated pll ? output frequency up to 125 mhz ? compatible with powerpc and pentium microprocessors ? 3.3v v cc ? + 100ps typical cycle?to?cycle jitter ? packaging (pb-free & green available): - 52-pin lqfp (fc) low voltage pll clock driver pin configuration 40 41 42 43 44 45 46 47 48 49 50 51 52 26 25 24 23 22 21 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 fselb1 fselb0 fsela1 fsela0 qa3 vcco qa2 gndo qa1 vcco qa0 gnd0 vco_sel fselfb1 qsync gndo qc0 vcco qc1 fselc0 fselc1 qc2 vcco qc3 gnd0 inv_clk gndo qb0 vcco qb1 gnd0 qb2 vcco qb3 ext_fb gndo qfb vcci fselfb0 gnd1 mr/oe frz_clk frz_data fselfb2 pll_en ref_sel tclk_sel tclk0 tclk1 xtal1 xtal2 vcca
2 ps8590c 09/22/04 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2972 low voltage pll clock driver block diagram vco phase detector v qa1 qa0 qa3 qa2 qb3 qb2 qb1 qb0 qc3 qc2 qc1 qc0 qsync qfb v v v sync frz 2 2 2 2 2 4, 6, 8, 12 4, 6, 8, 10 2, 4, 6, 8 4, 6, 8, 10 sync pulse data generator 0 d q d q 1 sync frz sync frz lpf 0 1 0 1 tclk1 tclk_sel ext_fb tclk0 pll_en ref_sel vc0_sel v d q fsela0:1 fselb0:1 fselc0:1 fselfbo:1 frz_clk frz_data inv_clk mr/oe fselfb2 power-on reset output disable circuitry v 12 v d q v d q d q sync frz sync frz xtal_1 xtal_2 v
3 ps8590c 09/22/04 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2972 low voltage pll clock driver function table 1 1 a l e s f0 a l e s fa q1 b l e s f0 b l e s fb q1 c l e s f0 c l e s fc q 0 0 1 1 0 1 0 1 4 6 8 2 1 0 0 1 1 0 1 0 1 4 6 8 0 1 0 0 1 1 0 1 0 1 2 4 6 8 2 b f l e s f1 b f l e s f0 b f l e s fb f q 0 0 0 0 0 0 1 1 0 1 0 1 4 6 8 0 1 1 1 1 1 0 0 1 1 0 1 0 1 8 2 1 6 1 0 2 n i p l o r t n o c' 0 ' c i g o l' 1 ' c i g o l l e s _ o c v l e s _ f e r l e s _ k l c t n e _ l l p e o / r m k l c _ v n i 2 / o c v k l c t 0 k l c t l l p s s a p y b z - i h t u p t u o / t e s e r r e t s a m 3 c q , 2 c q d e t r e v n i - n o n o c v l a t x 1 k l c t l l p e l b a n e s t u p t u o e l b a n e 3 c q , 2 c q d e t r e v n i function table 2 function table 3 s r e t e m a r a pe u l a v t u c l a t s y r ct u c t a l a t n e m a d n u f e c n a n o s e re c n a n o s e r l e l l a r a p e c a n r e l o t . q e r fc 5 2 @ m p p 0 0 1 y t i l i b a t s . p m e t . q e r f) c 0 7 o t 0 ( m p p 5 7 1 e g n a r g n i t a r e p oc 0 7 o t 0 e c n a t i c a p a c t n u h sf p 7 < r s em h o - 0 4 < l e v e l e v i r dw m 5 g n i g a) s r a e y 3 t s r i f ( r a e y / m p p 5 crystal recommendations
4 ps8590c 09/22/04 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2972 low voltage pll clock driver 1:1 mode 2:1 mode 3:1 mode 3:2 mode 4:1 mode 4:3 mode 1:6 mode fvco qa qc sync qa qc sync qc( 2) qa( 6) sync qa( 4) qc( 6) sync qc( 2) qa( 8) sync qa( 6) qc( 8) sync qa( 12) qc( 2) sync timing diagrams
5 ps8590c 09/22/04 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2972 low voltage pll clock driver l o b m y ss n o i t i d n o cc i t s i r e t c a r a h c. n i m. p y t. x a ms t i n u v h i e g a t l o v h g i h t u p n i0 . 26 . 3 v v l i e g a t l o v w o l t u p n i8 . 0 v h o i h o a m 0 2 = ) 2 ( e g a t l o v h g i h t u p t u o4 . 2 v l o i l o a m 0 2 = ) 2 ( e g a t l o v w o l t u p t u o5 . 0 i n i 3 e t o nt n e r r u c t u p n i0 2 1 i c c t n e r r u c y l p p u s t n e c s e i u q m u m i x a m0 9 15 1 2 a m i a c c v g o l a n a c c t n e r r u c5 10 2 c n i e c n a t i c a p a c t u p n i4 f p c d p t u p t u o r e pe c n a t i c a p a c n o i t a p i s s i d r e w o p5 2 notes: 1. v cmr is the difference from the most positive side of the differential input signal. normal operation is obtained when the ?high? input is within the v cmr range and the input lies within the v pp specification. 2. the pi6c2972 outputs can drive series or parallel terminated 50 ohm (or 50 ohm to v cc /2) transmission lines on the incident edge. 3. inputs have pull?up/pull?down resistors which affect input current. 4. special thermal handling may be required in some configurations. l o b m y sr e t e m a r a p. n i m. x a ms t i n u v c c e g a t l o v y l p p u s3 . 0 ?6 . 4v v i e g a t l o v t u p n i3 . 0 ?v d d 3 . 0 +v i n i t n e r r u c t u p n i0 2 a m t r o t s e r u t a r e p m e t e g a r o t s0 4 ?5 2 1c *absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute-maximum-rated conditions is not implied. dc characteristics (t a = 0c to 70c, v cc = 3.3v 5%) (4) absolute maximum ratings
6 ps8590c 09/22/04 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2972 low voltage pll clock driver notes: 7. 50 ohm transmission line terminated into v cc /2 8. tpd is specified for a 50 mhz input reference. the window will shrink/grow proportionally from the minimum limit with shorte r/ longer input reference periods. the tpd does not include jitter. l o b m y ss n o i t i d n o cs c i t s i r e t c a r a h c. n i m. x a ms t i n u f t , r ts l l a f / e s i r t u p n i k l c t0 . 3s n f e r f5 e t o ny c n e u q e r f t u p n i e c n e r e f e r5 e t o n5 e t o n , 0 0 1z h m c d f e r fe l c y c y t u d t u p n i e c n e r e f e r5 25 7% l a t x ty c n e u q e r f r o t a l l i c s o l a t s y r c0 15 2z h m pll input reference characteristic (t a = 0c to 70c) notes: 5. maximum input reference frequency is limited by the vco lock range and the feedback divider or 100 mhz, minimum input reference frequency is limited by the vco lock range and the feedback divider. l o b m y ss c i t s i r e t c a r a h cs n o i t i d n o c. n i m. p y t. x a ms t i n u t , r t f ) 7 e t o n ( e m i t l l a f / e s i r t u p t u ov 0 . 2 o t 8 . 05 1 . 02 . 1s n t w p ) 7 e t o n ( e l c y c y t u d t u p t u o t e l c y c 2 / 0 5 7 ? t e l c y c 2 / 0 0 5 t e l c y c 2 / 0 5 7 + s p t d p y a l e d n o i t a g a p o r p = b f q , 8 , 7 s e t o n 8 0 k l c t 1 k l c t 0 7 2 ? 0 3 3 ? 0 3 1 0 7 0 3 5 0 7 4 t s o w e k s t u p t u o - o t - t u p t u o7 e t o n0 5 5 f o c v e g n a r k c o l o c v 7 e t o n 0 0 20 8 4 z h m f x a m ) 2 ( q y c n e u q e r f t u p t u o m u m i x a m ) 4 ( q ) 6 ( q ) 8 ( q 5 2 1 0 2 1 0 8 0 6 r e t t i j t) k a e p ? o t ? k a e p ( r e t t i j e l c y c ? o t ? e l c y c 0 0 1 s p t z l p t , z h p e m i t e l b a s i d t u p t u o28 s n t l z p t , h z p e m i t e l b a n e t u p t u o20 1 t k c o l e m i t k c o l l l p m u m i x a m 0 1s m f x a m y c n e u q e r f k l c _ z r f m u m i x a m 0 2z h m ac characteristics (t a = 0c to 70c, v cc = 3.3v 5%)
7 ps8590c 09/22/04 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2972 low voltage pll clock driver packaging mechanical: 52-pin lqfp (fc) d0?d3 are the control bits for qa0?qa3, respectively d4?d7 are the control bits for qb0?qb3, respectively d8?d10 are the control bits for qc1?qc3, respectively d11 is the control bit for qsync freeze data input protocol t r a t s t i b 0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d0 1 d1 1 d seating plane 0.65 bsc .026 0.22 0.38 .009 .015 1.60 .063 1.35 1.45 .053 .057 0.05 0.15 .002 .006 x.xx x.xx denotes dimensions in millimeters 12.00 bsc .394 square 10.00 bsc .472 square gauge plane 1.00 ref .039 0.45 0.75 .018 .030 0.09 0.20 .004 .008 0.25 mm max. 0.10 .004 0 7 notes: 1. thermal characteristics can be found on the company web site at www.pericom.com/packaging/ pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com ordering information ordering code package code package type pi6c2972fc fc 52-pin lqfp PI6C2972FCE fc pb-free & green, 52-pin lqfp
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